Logic truth table evaluator
Restricted Boolean expression, input variables.
Digital logic and embedded systems ↗Digital logic and embedded systems calculators
25 calculators. Search or choose one below.
Calculators
Logic Karnaugh grouping worksheet
Minterms, don't-cares, variable count.
Digital logic and embedded systems ↗Logic Boolean equivalence checker
Two restricted expressions, variable limit.
Digital logic and embedded systems ↗Logic gate propagation path
Gate graph, supplied delays, input arrivals.
Digital logic and embedded systems ↗Logic setup-hold timing worksheet
Clock-data delays, device requirements, jitter.
Digital logic and embedded systems ↗Embedded timer prescaler selection
Clock, timer widths, target period, available prescalers.
Digital logic and embedded systems ↗Embedded UART baud divisor
Clock, divisor rules, target baud.
Digital logic and embedded systems ↗Embedded SPI transfer duration
Clock rate, payload bits, framing-idle gaps.
Digital logic and embedded systems ↗Embedded I2C bus transaction time
Clock, address-data bytes, acknowledgements, stretch assumption.
Digital logic and embedded systems ↗Embedded CAN frame bandwidth
Classic CAN data frames only (0–8 payload bytes), no CAN FD, remote frames, errors or retransmission.
Digital logic and embedded systems ↗Embedded standard CAN arbitration worksheet
Supported arbitration worksheet: distinct standard 11-bit classic CAN data identifiers, all ready at bus idle.
Digital logic and embedded systems ↗Embedded ADC code conversion
Reference voltage, resolution, input voltage, coding.
Digital logic and embedded systems ↗Embedded DAC output conversion
Reference, resolution, code, transfer convention.
Digital logic and embedded systems ↗Embedded fixed-point format range
Signedness, integer-fractional bits.
Digital logic and embedded systems ↗Embedded fixed-point arithmetic trace
Operands, formats, operation, rounding-saturation rules.
Digital logic and embedded systems ↗Embedded ring buffer sizing
Arrival-service traces, burst limits, element size.
Digital logic and embedded systems ↗Embedded DMA transfer schedule
Single shared nonpreemptive DMA bus, all supplied blocks ready at time zero.
Digital logic and embedded systems ↗Embedded watchdog timeout budget
Task timing bounds, kick points, supplied clock tolerance.
Digital logic and embedded systems ↗Embedded implicit-deadline task utilization
Independent periodic tasks with deadlines equal to periods, one ideal fully preemptive processor, no blocking or scheduling overhead.
Digital logic and embedded systems ↗Embedded stack usage aggregation
Call graph, frame sizes, recursion bounds.
Digital logic and embedded systems ↗Embedded flash partition layout
Image sizes, erase sectors, boot slots, reserve.
Digital logic and embedded systems ↗Embedded EEPROM wear budget
Writes per record, wear limit, leveling slots.
Digital logic and embedded systems ↗Embedded battery sleep-wake budget
Measured currents, duty phases, capacity.
Digital logic and embedded systems ↗Embedded checksum playground
Byte sequence, selected documented checksum parameters.
Digital logic and embedded systems ↗Embedded timestamp rollover
Counter width, clock frequency, start count.
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